Cache systems for processors often include buffers that are used to facilitate the handling of data that is being transferred between external memory and a memory cache. Caches are coupled to processors through higher speed internal bus connections and are used to reduce processing time required for processors to access and execute instructions. For some cache systems, linefill buffers and store buffers are used to facilitate instruction data transfer between external memory and caches.
FIG. 1 (Prior Art) is a block diagram of an example embodiment 100 for a cache system. A load/store unit 102, which communicates with a processor (not shown), provides control signals 121 to a cache controller (CTRL) 107 and control and/or data signals 120, 122, and 124 to a linefill buffer 108, a cache 106, and a store buffer 104, respectively. The cache 106 communicates data to and from the bus interface unit (BIU) 110 through connection 128. The cache 106 also sends data to the store buffer 104 using connection 132. The store buffer 104 sends data to the bus interface unit (BIU) 110 through connection 126. Linefill buffer 108 receives data from the bus interface unit (BIU) 110 through connection 130 and sends data to cache 106 through connection 134. The cache controller (CTRL) 107 provides control signals to the linefill buffer 108, the cache 106, and the store buffer 104. When bus access is desired, the store buffer 104, the cache 106, and the linefill buffer 108 provide bus request signals 140, 142, and 144 to multiplexer (MUX) 112, respectively. A request select (REQUEST SELECT) signal 116 is provided to multiplexer (MUX) 112 to determine which of the bus request signals 142, 144, and 146 is provided as the bus request (BUS REQUEST) signal 114 to the bus interface unit (BIU) 110. The bus interface unit (BIU) 110 communicates data to and from a main memory using a system bus coupled to connection 118.
During a linefill operation to transfer a cache line to the cache 106, the linefill buffer 108 is used to temporarily hold the cache line while it is in the process of being filled by a transfer of data from external memory. The linefill buffer 108 is a set of registers and is sized to hold address and data information for the cache line. The data is organized, for example, in double-word entries. The linefill buffer 108 also includes a set of status bits that are used to track the progress of the line. These status bits can include a valid bit and a busy bit. The valid bit indicates if the data within the linefill buffer 108 is valid, and the busy bit indicates if the linefill buffer 108 is still collecting data from the external system bus. When the linefill buffer 108 is no longer busy (i.e., data for the whole line has come back from the system bus), the cache line within the linefill buffer 108 is pushed into the cache array 106, and the status bits for the linefill buffer 108 are updated accordingly.
During the window of time when the linefill buffer 108 is still busy, a new load can be issued from the processor. If so, the load/store unit 102 and the cache 106 will target the line in the linefill buffer 108, and the data for that load will be supplied by the linefill buffer 108. Further, when the linefill buffer 108 is busy, the load/store unit 102 for the processor may issue a store that targets the linefill buffer 108. If this occurs, the cache controller (CTRL) 107 will perform operations to handle the requested store. First, the linefill buffer 108 captures the store data into the double-word entry targeted for the store and updates byte strobes for that entry to identify which bytes are valid. The byte strobes are additional status bits in the linefill buffer 108 that are used to remember valid store bytes because a store can be smaller than an entire double-word entry down to one byte. The next store, if targeting the same double-word entry, will override the data of the current byte strobes. Read data coming back from the bus for a linefill request can only be written to bytes that are not yet marked valid. The linefill buffer 108 uses these linefill mechanisms to gather the latest data from both the processor load/store unit 102 and the external bus prior to writing it into the cache 106.
After a store has written data into the linefill buffer 108, if the line is in write-through mode, the store can proceed to go out to the system bus or to the store buffer 104, depending on its attributes. This process will eventually be used to update the external memory with the latest data. This operation also ensures the coherency of the external memory and the contents of the cache 106. However, if the store writes to a copyback line in the linefill buffer 108, the cache controller (CTRL) 107 need not write the store out to the external bus. Instead the cache controller (CTRL) 107 can retire the store after writing it to the linefill buffer 108. Additionally, the cache controller (CTRL) 107 can mark the linefill buffer as dirty after this write, for example, by setting the dirty bit. The dirty bit is an additional status bit in the linefill buffer 108. Dirty bits are also part of the cache line status bits that are stored for cache lines in the cache 106. When set, the dirty bit indicates that the data in the cache line is newer data as compared to the data stored in the main memory.
Once the linefill buffer 108 has received all of the data from the system bus for the linefill request, it pushes the cache line into the cache 106 and invalidates the data within linefill buffer 108. Subsequent loads and stores which are hitting that cache line will be directed to the cache 106 and not the linefill buffer 108. If an event, such as a bus failure, prevents the system bus from returning all of the data to the linefill buffer 108 as part of the linefill request, the contents of the linefill buffer 108 are discarded. However, this discarding of contents of the linefill buffer 108 creates a problem if the linefill buffer 108 is dirty (e.g., holding data that is newer than the data in the external memory). If the dirty data within the linefill buffer 108 is discarded, then the most recent data is lost.
Although bus failure events during a linefill request are unlikely to occur, some applications (e.g., medical and automotive applications) require a high level of failure recovery that would include recovery of dirty data within the linefill buffer during such a bus failure. FIG. 1 (Prior Art) addresses this potential loss of dirty data by always storing a copy of the linefill buffer 108 in the store buffer 104 during a linefill request. This linefill buffer copy (LFB COPY) 136, however, takes up cache lines within the store buffer 104 and can delay other operations of the store buffer 104 as the store buffer 104 waits for the linefill request to complete. In particular, the contents of the store buffer 104 are primarily used for store operations by the load/store unit 102. Thus, while the LFB COPY 136 stored in the store buffer 104 protects against loss of dirty linefill data within linefill buffer 108, this LFB COPY 136 also reduces the efficiency of the store buffer 104 by taking up cache lines within the store buffer 104 and potentially stalling the store operations for the store buffer 108.